AOD4130/aoi4130 60v n-channel mosfet general description product summary v ds i d (at v gs =10v) 30a r ds(on) (at v gs =10v) < 24m w r ds(on) (at v gs =4.5v) < 30m w 100% uis tested 100% r g tested symbol v ds v gs i dm i as , i ar e as , e ar t j , t stg symbol t 10s steady-state steady-state r q jc maximum junction-to-case c/w c/w maximum junction-to-ambient a d 2.4 50 2.9 power dissipation b p d w power dissipation a p dsm w t a =70c 52 1.6 t a =25c a t a =25c i dsm a t a =70c i d 30 20 t c =25c t c =100c avalanche energy l=0.1mh c mj avalanche current c 5 continuous drain current 36.5 6.5 a 27 the AOD4130/aoi4130 combines advanced trench mosfet technology with a low resistance package to provide extremely low r ds(on) . this device is ideal for boost converters and synchronous rectifiers for consumer, telecom, industrial power supplies and le d backlighting. v maximum units parameter absolute maximum ratings t a =25c unless otherwise noted 60v v 20 gate-source voltage drain-source voltage 60 units maximum junction-to-ambient a c/w r q ja 12.4 34 20 junction and storage temperature range -55 to 175 c thermal characteristics 74 pulsed drain current c continuous drain current parameter typ max t c =25c 2.5 25 t c =100c g ds g g d d s s d top view bottom view to-251a ipak to252 dpak topview bottom view g g d d s s d rev 1: june 2011 www.aosmd.com page 1 of 6
AOD4130/aoi4130 symbol min typ max units bv dss 60 v v ds =60v, v gs =0v 1 t j =55c 5 i gss 100 na v gs(th) gate threshold voltage 1.6 2.2 2.8 v i d(on) 74 a 19.5 24 t j =125c 37.5 45 24 30 m w g fs 55 s v sd 0.76 1 v i s 46 a c iss 1265 1582 1900 pf c oss 70 100 130 pf c rss 40 67 95 pf r g 1.8 3.6 5.4 w q g (10v) 23 28.3 34 nc q g (4.5v) 11 13.4 16 nc q gs 3.6 4.5 5.4 nc q gd 4.3 7.2 10 nc t d(on) 7.5 ns t r 6.5 ns t d(off) 33 ns t f 7.5 ns t rr 15 22 30 ns q rr 53 76 100 nc this product has been designed and qualified for th e consumer market. applications or uses as critical components in life support devices or systems are n ot authorized. aos does not assume any liability ar ising out of such applications or uses of its products. aos reserves the right to improve product design, functions and reliability without notice. body diode reverse recovery time drain-source breakdown voltage on state drain current i d =250 m a, v gs =0v v gs =10v, v ds =5v v gs =10v, i d =20a reverse transfer capacitance i f =20a, di/dt=500a/ m s v gs =0v, v ds =30v, f=1mhz switching parameters electrical characteristics (t j =25c unless otherwise noted) static parameters parameter conditions i dss m a v ds =5v, i d =250 m a v ds =0v, v gs = 20v zero gate voltage drain current gate-body leakage current forward transconductance diode forward voltage r ds(on) static drain-source on-resistance m w i s =1a,v gs =0v v ds =5v, i d =20a v gs =4.5v, i d =20a v gs =10v, v ds =30v, r l =1.5 w , r gen =3 w gate resistance v gs =0v, v ds =0v, f=1mhz turn-off fall time total gate charge v gs =10v, v ds =30v, i d =20a gate source charge gate drain charge total gate charge body diode reverse recovery charge i f =20a, di/dt=500a/ m s maximum body-diode continuous current g input capacitance output capacitance turn-on delaytime dynamic parameters turn-on rise time turn-off delaytime a. the value of r q ja is measured with the device mounted on 1in 2 fr-4 board with 2oz. copper, in a still air enviro nment with t a =25c. the power dissipation p dsm is based on r q ja and the maximum allowed junction temperature of 15 0c. the value in any given application depends on the user's specific board design, and the maximu m temperature of 175c may be used if the pcb allow s it. b. the power dissipation p d is based on t j(max) =175c, using junction-to-case thermal resistance, and is more useful in setting the upper dissipation limit for cases where additional heatsi nking is used. c. repetitive rating, pulse width limited by juncti on temperature t j(max) =175c. ratings are based on low frequency and duty cycles to keep initial t j =25c. d. the r q ja is the sum of the thermal impedance from junction to case r q jc and case to ambient. e. the static characteristics in figures 1 to 6 are obtained using <300 m s pulses, duty cycle 0.5% max. f. these curves are based on the junction-to-case t hermal impedance which is measured with the device mounted to a large heatsink, assuming a maximum junction temperature of t j(max) =175c. the soa curve provides a single pulse ratin g. g. the maximum current rating is package limited. h. these tests are performed with the device mounte d on 1 in 2 fr-4 board with 2oz. copper, in a still air enviro nment with t a =25c. rev 1: june 2011 www.aosmd.com page 2 of 6
AOD4130/aoi4130 typical electrical and thermal characteristics 17 52 10 0 18 40 0 20 40 60 80 0 1 2 3 4 5 6 v gs (volts) figure 2: transfer characteristics (note e) i d (a) 10 15 20 25 30 0 5 10 15 20 25 30 i d (a) figure 3: on-resistance vs. drain current and gate voltage (note e) r ds(on) (m w ww w ) 1.0e-05 1.0e-04 1.0e-03 1.0e-02 1.0e-01 1.0e+00 1.0e+01 1.0e+02 0.0 0.2 0.4 0.6 0.8 1.0 1.2 v sd (volts) figure 6: body-diode characteristics (note e) i s (a) 25c 125c 0.8 1.2 1.6 2 2.4 2.8 0 25 50 75 100 125 150 175 200 temperature (c) figure 4: on-resistance vs. junction temperature (note e) normalized on-resistance v gs =4.5v i d =20a v gs =10v i d =20a 0 10 20 30 40 50 60 2 4 6 8 10 v gs (volts) figure 5: on-resistance vs. gate-source voltage (note e) r ds(on) (m w ww w ) 25c 125c v ds =5v v gs =4.5v v gs =10v i d =20a 25c 125c 0 20 40 60 80 0 1 2 3 4 5 v ds (volts) fig 1: on-region characteristics (note e) i d (a) v gs =3.5v 4v 6v 10v 4.5v rev 1: june 2011 www.aosmd.com page 3 of 6
AOD4130/aoi4130 typical electrical and thermal characteristics 17 52 10 0 18 40 0 2 4 6 8 10 0 5 10 15 20 25 30 q g (nc) figure 7: gate-charge characteristics v gs (volts) 0 500 1000 1500 2000 2500 0 10 20 30 40 50 60 v ds (volts) figure 8: capacitance characteristics capacitance (pf) c iss 0 100 200 300 400 500 0.0001 0.001 0.01 0.1 1 10 pulse width (s) figure 10: single pulse power rating junction-to- case (note f) power (w) 0.001 0.01 0.1 1 10 0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 pulse width (s) figure 11: normalized maximum transient thermal imp edance (note f) z q qq q jc normalized transient thermal resistance c oss c rss v ds =30v i d =20a single pulse d=t on /t t j,pk =t c +p dm .z q jc .r q jc t on t p d in descending order d=0.5, 0.3, 0.1, 0.05, 0.02, 0.01, single pulse t j(max) =175c t c =25c 10 m s 0.0 0.1 1.0 10.0 100.0 1000.0 0.01 0.1 1 10 100 v ds (volts) i d (amps) figure 9: maximum forward biased safe operating area (note f) 10 m s 1ms dc r ds(on) limited t j(max) =175c t c =25c 100 m s r q jc =2.9c/w rev 1: june 2011 www.aosmd.com page 4 of 6
AOD4130/aoi4130 typical electrical and thermal characteristics 17 52 10 0 18 40 0.001 0.01 0.1 1 10 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000 pulse width (s) figure 16: normalized maximum transient thermal imp edance (note h) z q qq q ja normalized transient thermal resistance single pulse d=t on /t t j,pk =t a +p dm .z q ja .r q ja t on t p d in descending order d=0.5, 0.3, 0.1, 0.05, 0.02, 0.01, single pulse 0 10 20 30 40 50 60 0 25 50 75 100 125 150 175 t case (c) figure 13: power de-rating (note f) power dissipation (w) 0 5 10 15 20 25 30 35 0 25 50 75 100 125 150 175 t case (c) figure 14: current de-rating (note f) current rating i d (a) 1 10 100 1000 10000 0.00001 0.001 0.1 10 1000 pulse width (s) figure 15: single pulse power rating junction-to- ambient (note h) power (w) t a =25c r q ja =50c/w 10 100 1 10 100 1000 time in avalanche, t a ( m mm m s) figure 12: single pulse avalanche capability (note c) i ar (a) peak avalanche current t a =25c t a =150c t a =100c t a =125c rev 1: june 2011 www.aosmd.com page 5 of 6
AOD4130/aoi4130 - + vdc ig vds dut - + vdc vgs vgs 10v qg qgs qgd charge gate charge test circuit & waveform - + vdc dut vdd vgs vds vgs rl rg vgs vds 10% 90% resistive switching test circuit & waveforms t t r d(on) t on t d(off) t f t off vdd vgs id vgs rg dut - + vdc l vgs vds id vgs bv i unclamped inductive switching (uis) test circuit & waveforms ig vgs - + vdc dut l vds vgs vds isd isd diode recovery test circuit & waveforms vds - vds + i f ar dss 2 e = 1/2 li di/dt i rm rr vdd vdd q = - idt ar ar t rr rev 1: june 2011 www.aosmd.com page 6 of 6
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